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128k-Byte Processor Instruction Address Space for Each Level Status Block

IP.com Disclosure Number: IPCOM000040672D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+4]

Abstract

This article describes a technique for a processor which provides larger than 64KB instruction address spaces while maintaining compatibility for existing 64KB instruction address spaces concurrently in the same system. Each program represented by a level status block (LSB) may fetch instructions using the entire 16-bit instruction address as a word address rather than a byte address. When Instruction Word Addressing is enabled, the instruction address space is doubled to 128KB or 64K words. In the technique disclosed herein, a bit in the level status register (LSR) bit 12, which is part of the LSB, is used to enable Instruction Word Addressing, which provides compatibility for existing programs and applications that use Instruction Byte Addressing.

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128k-Byte Processor Instruction Address Space for Each Level Status Block

This article describes a technique for a processor which provides larger than 64KB instruction address spaces while maintaining compatibility for existing 64KB instruction address spaces concurrently in the same system. Each program represented by a level status block (LSB) may fetch instructions using the entire 16-bit instruction address as a word address rather than a byte address. When Instruction Word Addressing is enabled, the instruction address space is doubled to 128KB or 64K words. In the technique disclosed herein, a bit in the level status register (LSR) bit 12, which is part of the LSB, is used to enable Instruction Word Addressing, which provides compatibility for existing programs and applications that use Instruction Byte Addressing. This allows the system to run a mixture of programs which are fetching instructions using Instruction Byte Addressing while others are using Instruction Word Addressing. Interrupt handler/device handler compatibility is ensured by using Instruction Byte Addressing when vectoring to the interrupt handler and then allowing the interrupt handler to use the Set Level Block (SELB) instruction to change to Instruction Word Addressing, if desired. An example of where this technique could be implemented is in an IBM Series/1 processor which has the appropriate facilities in its base architecture to do this.

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