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Extended Logical Address Space for Each Level Status Block of 16-Bit Computers

IP.com Disclosure Number: IPCOM000040676D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 47K

Publishing Venue

IBM

Related People

Bourke, DG: AUTHOR [+4]

Abstract

A technique is described whereby the addressing capability of a program for computers, with 16-bit logical addressing and segmented address translation, is extended up to 64 megabytes of storage. The concept provides 26-bit extended addresses which are translated to 16-bit addresses for manipulation by the standard 16-bit instruction set and addressing modes. The concept also provides a method of recognizing disk page faults, thereby eliminating the need to make the entire instruction set restartable. As an example, the IBM Series/1 uses an extended level status block (LSB) containing an address space key and an address pointer to a logical segment table (LST).

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Extended Logical Address Space for Each Level Status Block of 16-Bit Computers

A technique is described whereby the addressing capability of a program for computers, with 16-bit logical addressing and segmented address translation, is extended up to 64 megabytes of storage. The concept provides 26-bit extended addresses which are translated to 16-bit addresses for manipulation by the standard 16-bit instruction set and addressing modes. The concept also provides a method of recognizing disk page faults, thereby eliminating the need to make the entire instruction set restartable. As an example, the IBM Series/1 uses an extended level status block (LSB) containing an address space key and an address pointer to a logical segment table (LST). The LST along with a new non- privileged instruction called MXALR provide the ability to translate a 26-bit extended logical address into 16-bit addresses and to load the appropriate segment registers in instruction or data address spaces. This provides the support for an extended logical address space (ELAS), as large as 64 megabytes, for each program represented by an extended LSB in the system. A program can be written with data, or program instructions, in a logically large address space appearing to be unconstrained by the 16-bit addressing boundary. The actual data or instructions may have been loaded into main storage, not currently addressable by the program. Prior to referencing data or instructions, a MXALR instruction is executed so as to enable data or instructions to be addressable in a normal sixteen bit data or instruction address space. Once mapped into a sixteen bit address range, the other instructions may then access the data using the sixteen bit addressing modes. Addresses in the ELAS are represented by a four-byte pointer, composed of a 15-bit logic segment number (LSN) and an 11-bit byte offset. The 15-bit LSN is used to index into the LST to find a segment register entry which is to be loaded. Loading the segment register enables data or instructions to be accessible through the 16-bit address translation, requiring no change in the instruction set. Upon indexing into the LST, the valid bit is checked, and if it is off, indicating that the two kiloby...