Browse Prior Art Database

Large Virtual Storage for Arrays

IP.com Disclosure Number: IPCOM000040677D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 25K

Publishing Venue

IBM

Related People

Brady, JT: AUTHOR

Abstract

A method is described for increasing virtual address space for data arrays. In the IBM System/370, extension of translation can be accomplished by changing the definition of control registers for the Segment Table Origin (STO). The current definition, as illustrated in Fig. 1, does not use bits 20-24. These unused bits can be used to extend the Primary/Secondary Segment Table Length (P/S STL) field to 12 bits, allowing 64 gigabytes addressability. Alternatively, the P/S STL field can be expanded, as shown in Fig. 2, to incorporate only bits 21-24, leaving bit 20 as a mode bit which changes segment table increments to a value other than the current value of 16. As an example, if the segment table increment is changed to 2048, the P/S STL field could then allow 8 terabytes of virtual addressing.

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Large Virtual Storage for Arrays

A method is described for increasing virtual address space for data arrays. In the IBM System/370, extension of translation can be accomplished by changing the definition of control registers for the Segment Table Origin (STO). The current definition, as illustrated in Fig. 1, does not use bits 20-24. These unused bits can be used to extend the Primary/Secondary Segment Table Length (P/S STL) field to 12 bits, allowing 64 gigabytes addressability. Alternatively, the P/S STL field can be expanded, as shown in Fig. 2, to incorporate only bits 21-24, leaving bit 20 as a mode bit which changes segment table increments to a value other than the current value of 16. As an example, if the segment table increment is changed to 2048, the P/S STL field could then allow 8 terabytes of virtual addressing. In architectures such as the IBM System/370, separate (index) fields are provided in instruction to specify registers that are used for indexing. The (index) registers specified by these fields can be implemented in an arbitrary width (e.g., 64 bits). A new set of instructions is implemented to load, store, increment and test this new set of (index) registers.

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