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Method for Improving Geometric Packaging of Circuit Chip Modules: Utilizing Top-Down Slicing-Based Floorplanning

IP.com Disclosure Number: IPCOM000040679D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 34K

Publishing Venue

IBM

Related People

LaPotin, DP: AUTHOR

Abstract

A technique is described whereby the top-down floorplanning approach to geometric packaging of integrated circuit (IC) modules is improved by optimizing the topology while considering the geometry and connectivity of the modules. The approach is particularly well suited to designs which contain a predominance of fixed shaped components, such as datapaths, gate arrays and predefined library modules. Floorplanning can be considered as the assignment of circuit components or modules to a chip image, subject to electrical and physical constraints, and occurs during the early stages of the integrated circuit (IC) design process. A number of floorplanning methods have been derived, such as bottom-up, top-down partitioning and flat approaches.

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Method for Improving Geometric Packaging of Circuit Chip Modules: Utilizing Top-Down Slicing-Based Floorplanning

A technique is described whereby the top-down floorplanning approach to geometric packaging of integrated circuit (IC) modules is improved by optimizing the topology while considering the geometry and connectivity of the modules. The approach is particularly well suited to designs which contain a predominance of fixed shaped components, such as datapaths, gate arrays and predefined library modules. Floorplanning can be considered as the assignment of circuit components or modules to a chip image, subject to electrical and physical constraints, and occurs during the early stages of the integrated circuit (IC) design process. A number of floorplanning methods have been derived, such as bottom-up, top-down partitioning and flat approaches. Top-down and flat approaches are generally preferred, since they support a more global view of floorplanning. A top-down approach offers a complexity advantage over a flat approach by decomposing the floorplanning task into a number of smaller subtasks, for example via bipartitioning techniques. Geometric issues must be considered in conjunction with topological decisions in order to obtain dense layouts. An example would be the floorplanning of datapaths, regular images, such as gate arrays and predefined library modules. The top-down floorplanning method described herein utilizes topological decisions based on geometry, as well as standard metrics, such as connectivity and area. It is particularly well suited to designs consisting of a predominance of fixed-shape components. A specific implementation is described in terms of top-down floorplanning via bipartitioning and slicing techniques. In prior art, slicing-based floorplanning approaches typically implemented slice-line directions, so chosen to alternate between the horizontal and vertical at successive bipartitioning steps. Such sequences were believed to be the least restrictive, in terms of wiring, and non- restrictive in terms of area utilization, assuming that modules have a wide degree of flexibility. Determining module orientation at each bipartitioning step utilized top or bottom of a horizontal slice line or left or right of a vertical slice line via in- place partitioning techniques employing boundary-condition inherences. A slicing tree data structure is typically used for representing bipartitioning sequences and has efficient algorithms devised for mapping the slicing tree onto a floorplan consisting of a geometric placement of modules. For a given slicing-tree topology and set of module dimensions, such algorithms will produce a set of possible floorplan outer dimensions. Each of the floorplan dimensions has the same topology, while the individual module dimensions can differ. In the case of a slicing tree where each module or leaf node has one possible dimension, the algorithms will produce a single floorplan outer d...