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Floorplanning Method for Semi-Custom VLSI Chips

IP.com Disclosure Number: IPCOM000040691D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 4 page(s) / 52K

Publishing Venue

IBM

Related People

Cagle, JW: AUTHOR [+4]

Abstract

A method of chip floorplanning that is better suited to semi-custom VLSI chips than previous state-of-the-art methods is described. (Image Omitted) Floor planning in VLSI design is necessary in order to achieve smaller chip sizes. Existing state-of-the-art floorplanning tools either assume that all logic blocks are of a constant size and shape, or that all logic macro sizings are to be decided by the floorplanning program. Neither of these cases is true in semi-custom VLSI chips, where the chip consists of both predefined (Dataflow) macros and undefined (Random Logic) macros. Dataflow macros are bit-oriented logic functions that deal with busses of signals, such as a 32-bit register. Since these types of macros can be extremely common, they are physically implemented in advance of chip logic completion.

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Floorplanning Method for Semi-Custom VLSI Chips

A method of chip floorplanning that is better suited to semi-custom VLSI chips than previous state-of-the-art methods is described.

(Image Omitted)

Floor planning in VLSI design is necessary in order to achieve smaller chip sizes. Existing state-of-the-art floorplanning tools either assume that all logic blocks are of a constant size and shape, or that all logic macro sizings are to be decided by the floorplanning program. Neither of these cases is true in semi-custom VLSI chips, where the chip consists of both predefined (Dataflow) macros and undefined (Random Logic) macros. Dataflow macros are bit-oriented logic functions that deal with busses of signals, such as a 32-bit register. Since these types of macros can be extremely common, they are physically implemented in advance of chip logic completion. Because of this, dataflow macro dimensions, permeability and I/O accessibility are known before chip floorplanning begins. Some examples of dataflow macros are: an 8-bit multiplexer, 16-bit RAM, and a 32-bit register file. Random Logic Macros (RLMs) are not bit-oriented, and their exact logical contents remain unknown until after chip logic is complete. At the floorplanning stage, only the circuit area required to build the RLM is known. For each RLM, the floorplanning program must determine the best macro dimensions, I/O positions, and placement on the chip. An example of an RLM is a collection of miscellaneous logic for chip clocking. Attempts to use existing floorplanning tools in the semi-custom environment have given unrealistic solutions in terms of macro sizings, wiring area utilization, and chip dimension. The method assumes a column-oriented approach to chip floorplanning and performs well irrespective of the mix of macro types. The chip will consist of a user-defined number of columns, or "stacks," that all macros must be within. Each column has a width in channels associated with it; a macro may not be placed within a column whose width is less than the macro width. Macros that have no dimensions upon entering the floorplanner (RLMs) will have dimensions that are a function of their circuit area and the width of the column they are in. Inter-column wiring communication is done via traffic busses whose positions are user-defined. The macros are placed upon the chip by the floorplanning program such that all macros may be wired together without excessive congestion or wasted chip area. An example of a chip floorplan done by this method can be seen in Fig. 1. The floorplanning method is separated into many phases and discussed in this manner. The phases are: . Input Phase

. Column Partitioning Phase

. Horizontal Column Ordering Phase

. Vertical Column Ordering Phase (independent)

. Vertical Column Ordering Phase (dependent)

1

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. Output Phase INPUT PHASE The input data desired by this floorplanning method is primarily the same as in state-of-the-art chip planning too...