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Multi-Select Tolerant Shift Register Latch

IP.com Disclosure Number: IPCOM000040718D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Loehlein, WD: AUTHOR [+2]

Abstract

The multi-select tolerant shift register latch, described in this article, has the advantage that it is much faster than existing latches and that its improved function and test coverage is obtained without logic changes. The illustrated latch has several data/gate inputs D and G. Simultaneous selection of gates 1 and 2 in such latches produces a DC current which leads to power and reliability problems particularly during testing. For simultaneous selection (G1 and G2 active) and D1 = "1" and D2 = "0", a path on the left and the right latch side is activated. In this case, transistors T1, T2 and T8, T6 are conducting, leading to an undefined state in the latch and a DC current path. This is avoided if clock generation is inhibited for the simultaneous activation of G1 and G2.

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Multi-Select Tolerant Shift Register Latch

The multi-select tolerant shift register latch, described in this article, has the advantage that it is much faster than existing latches and that its improved function and test coverage is obtained without logic changes. The illustrated latch has several data/gate inputs D and G. Simultaneous selection of gates 1 and 2 in such latches produces a DC current which leads to power and reliability problems particularly during testing. For simultaneous selection (G1 and G2 active) and D1 = "1" and D2 = "0", a path on the left and the right latch side is activated. In this case, transistors T1, T2 and T8, T6 are conducting, leading to an undefined state in the latch and a DC current path. This is avoided if clock generation is inhibited for the simultaneous activation of G1 and G2.

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