Browse Prior Art Database

Higher Level Subroutines Invoked on Behalf of Horizontal Microcode

IP.com Disclosure Number: IPCOM000040721D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 13K

Publishing Venue

IBM

Related People

Frye, HE: AUTHOR [+3]

Abstract

By use of a programmable register bit, Internal Microprogram Interface (IMPI) subroutines are invoked on behalf of Horizonal Microcode (HMC) in a manner transparent to Vertical Microcode (VMC). In order to be transparent to VMC, no exceptions or task switching can be allowed during the execution of an IMPI subroutine for HMC. Exceptions which occur during an IMPI instruction indicate conditions which, in general, cannot be ignored. These include such things as page faults, invalid decimal data, and effective address overflow. Some of these can be avoided by doing checks in HMC prior to invoking an IMPI subroutine. Some of them, such as page faults, can be handled when they occur either by passing the exception back to VMC or by invoking a machine check.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 51% of the total text.

Page 1 of 2

Higher Level Subroutines Invoked on Behalf of Horizontal Microcode

By use of a programmable register bit, Internal Microprogram Interface (IMPI) subroutines are invoked on behalf of Horizonal Microcode (HMC) in a manner transparent to Vertical Microcode (VMC). In order to be transparent to VMC, no exceptions or task switching can be allowed during the execution of an IMPI subroutine for HMC. Exceptions which occur during an IMPI instruction indicate conditions which, in general, cannot be ignored. These include such things as page faults, invalid decimal data, and effective address overflow. Some of these can be avoided by doing checks in HMC prior to invoking an IMPI subroutine. Some of them, such as page faults, can be handled when they occur either by passing the exception back to VMC or by invoking a machine check. Exceptions which occur at the end of an instruction or between instructions are not normally related to the instruction, but are asynchronous, such as I/O or timer events. While these exceptions cannot be ignored, they can be deferred. An exception (EX) register contains several bits which indicate that an exception condition needs to be processed. When the HMC indicates that an IMPI instruction has completed by issuing an ENDOP instruction, an HMC trap will occur if any of the EX register bits are nonzero. Some of the EX register bits are set by hardware to indicate that an I/O event needs service. This invention gates the HMC trap on ENDOP with a hardware latch which can be set and reset by HMC. This latch is bit 1 of a general- purpose register referred to as a G register. When the HMC sets bit 1 of the G register to the "on" state, no HMC trap will occur on an ENDOP even if one or more of the EX register bits are on. When the HMC later resets bit 1 of the G register, HMC traps will occur if any of the EX register bits are on. When HMC wishes to execute an IMPI subroutine, the current IMPI registers, IAR (IMPI instruction address register), and condition code are saved in an HMC reserved area of main storage. Then the G register bit 1 is set on. The address of an IMPI subroutine is th...