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Direct Memory Access Channel Sharing Mechanism

IP.com Disclosure Number: IPCOM000040729D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 34K

Publishing Venue

IBM

Related People

Batalden, GD: AUTHOR [+4]

Abstract

This mechanism facilitates the effective use of a limited number of Direct Memory Access (DMA) channels by a larger number of independent I/O devices. The result is that the I/O devices are still able to transfer data in a timely manner while the overall cost and complexity of the hardware is reduced. In addition, the sharing technique results in more uniform and consistent time required to service I/O requests. This mechanism requires I/O device hardware which can dynamically be assigned to any of the DMA data channels. A bus in the IBM Personal Computer Family II is an example of a bus which supports this type of dynamic assignment. It is possible to accommodate devices with limited or no flexibility, but this reduces the overall effectiveness of this mechanism.

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Direct Memory Access Channel Sharing Mechanism

This mechanism facilitates the effective use of a limited number of Direct Memory Access (DMA) channels by a larger number of independent I/O devices. The result is that the I/O devices are still able to transfer data in a timely manner while the overall cost and complexity of the hardware is reduced. In addition, the sharing technique results in more uniform and consistent time required to service I/O requests. This mechanism requires I/O device hardware which can dynamically be assigned to any of the DMA data channels. A bus in the IBM Personal Computer Family II is an example of a bus which supports this type of dynamic assignment. It is possible to accommodate devices with limited or no flexibility, but this reduces the overall effectiveness of this mechanism. Given that the total number of DMA channels available is a relatively small, fixed number, a simple list in storage is allocated. This list has room for one entry for each of the DMA channels (see Fig. 1). The entries in this DMA channel list are used to record the current status of each DMA channel. Zero indicates not in use, while any other value specifies the current "owner" of the channel. To dynamically allocate DMA channels, the allocation scheme must obviously be fast and efficient. Speed is essential to dynamically al- locate DMA channels because a computer system will typically perform a very large number of DMA operations. Even small amounts of overhead in such a heavily utilized path could affect overall system performance. With a small, fixed-size list, a very fast scheme can be implemented with a simple linear search. When a channel is required, the list is searched sequentially until a free channel...