Browse Prior Art Database

Method to Provide a Selectable ADDRESS RANGE for Display Adapter Card

IP.com Disclosure Number: IPCOM000040732D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Romero, HG: AUTHOR [+2]

Abstract

The figure is a functional block diagram of an addressing circuit for an adapter card in which the address space required for the display to reside in is 256K bytes. Two different beginning address spaces had to be assigned to the display so that it could function in two different Personal Computer (PC) systems. With one system the display memory area is located in the crowded address space below 1 Megabyte at 0C0000 Hex address. In the second system the display memory area is located above 1 Megabyte at C00000 Hex address. All the memory space address decoding for the display is done in Programmable Array Logic (PAL). Functionally, the PAL creates two address decodes by using System Address lines 23 thru 17 (+SA23...+SA17). Another input to the PAL is + SELECT ADDRESS RANGE.

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Method to Provide a Selectable ADDRESS RANGE for Display Adapter Card

The figure is a functional block diagram of an addressing circuit for an adapter card in which the address space required for the display to reside in is 256K bytes. Two different beginning address spaces had to be assigned to the display so that it could function in two different Personal Computer (PC) systems. With one system the display memory area is located in the crowded address space below 1 Megabyte at 0C0000 Hex address. In the second system the display memory area is located above 1 Megabyte at C00000 Hex address. All the memory space address decoding for the display is done in Programmable Array Logic (PAL). Functionally, the PAL creates two address decodes by using System Address lines 23 thru 17 (+SA23...+SA17). Another input to the PAL is + SELECT ADDRESS RANGE. This input comes from a register that is controlled by system software. The system therefore can decide whether the display decodes either the first or second memory space address by loading the register with the appropriate value. The + SELECT ADDRESS RANGE signal acts as a select line in a 2 to 1 multiplexer whose two inputs are the address decodes used to differentiate between the first and second system. The remaining two inputs are System Memory Read (-SMEMR) and System Memory Write (-SMEMW). These two inputs are combined with the output of the multiplexer in order to create a memory decode signal (-MEMDEC) for the di...