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Transient Terminator for Transmission Lines

IP.com Disclosure Number: IPCOM000040739D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Ludwig, T: AUTHOR [+3]

Abstract

High-speed signal transmission through transmission lines requires proper line termination to prevent oscillations on a line. Existing terminators are subject to high current and power dissipation. The transient terminator, described in this article, is applied only for a short time to absorb the energy in the transmission line that causes oscillations. Fig. 1 shows one example of the transient terminator. The transmission line is connected to the chip-in pad and terminated by a first pair of FET transistors T1, T2, connected to high potential VH, and by a second pair of FET transistors T3, T4, connected to ground. T1 and T2 are P-type, and T3 and T4 are N-type FETs.

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Transient Terminator for Transmission Lines

High-speed signal transmission through transmission lines requires proper line termination to prevent oscillations on a line. Existing terminators are subject to high current and power dissipation. The transient terminator, described in this article, is applied only for a short time to absorb the energy in the transmission line that causes oscillations. Fig. 1 shows one example of the transient terminator. The transmission line is connected to the chip-in pad and terminated by a first pair of FET transistors T1, T2, connected to high potential VH, and by a second pair of FET transistors T3, T4, connected to ground. T1 and T2 are P-type, and T3 and T4 are N-type FETs. T2 and T3 are directly controlled by the complementary output C of receiver REC and T1 and T4 by a delayed signal Cd, with the FET gates being connected to C via a delay line which has an inverting function. A steady down or up level of the chip-in pad has the following effect on the gate potentials Vg: CHIP-IN = 0 (down level) VgT4 = 0 T T4 = OFF

VgT2 = 1 T T2 = OFF

both paths to VH and GND

are off CHIP-IN = 1 (up level)

VgT3 = 0 T T3 = OFF

VgT1 = 1 T T1 = OFF

both paths to VH and GND

are off This shows that in the steady state both terminator FET pairs are turned off. Immediately after the chip-in pad changes its state, one transistor pair turns on for the time for which the pulse is delayed by the delay line. When the transition of C arrives at output Cd of the delay line, the conductive transistor pair is turned off. For the up-going transition, T1 and T2 are turned on. The resistivity of the two transistors is designed such that the sum of their internal resistors matches the transmission line impedance. For a short time, as defined by the delay line, the respective t...