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Integrated Single Shot

IP.com Disclosure Number: IPCOM000040747D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 43K

Publishing Venue

IBM

Related People

Jaworski, RC: AUTHOR [+3]

Abstract

Logic transitions of either polarity can be converted to accurate time interval logic pulses without the use of a special integrated capacitor device. A pair of NPN or PNP devices, such as NPN transistors QA and QB in Fig. 1, acts as the capacitor. The pulse resulting from a (Image Omitted) positive input transition is closely matched in time duration to the pulse resulting from a negative input transition. Because the single shot capacitor can be implemented with standard devices, no external capacitor is required. The internal capacitor also eliminates the large parasitic pin capacitances that reduce the swing across the differential capacitor via capacitive voltage division. The net result is that the precious Input/Output pins are saved for other uses. Fig.

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Integrated Single Shot

Logic transitions of either polarity can be converted to accurate time interval logic pulses without the use of a special integrated capacitor device. A pair of NPN or PNP devices, such as NPN transistors QA and QB in Fig. 1, acts as the capacitor. The pulse resulting from a

(Image Omitted)

positive input transition is closely matched in time duration to the pulse resulting from a negative input transition. Because the single shot capacitor can be implemented with standard devices, no external capacitor is required. The internal capacitor also eliminates the large parasitic pin capacitances that reduce the swing across the differential capacitor via capacitive voltage division. The net result is that the precious Input/Output pins are saved for other uses. Fig. 1 shows a schematic of the basic two-device differential capacitor produced from two NPN transistors QA and QB, and Fig. 2 shows an equivalent circuit. The Fig. 2 circuit shows the various parasitic diodes that in effect exist in the Fig. 1 basic circuit. The terminals CAP1 and CAP2 in Fig. 1 and the equivalent terminals CB1-E2 and CB2-E1 are connected between connectors C0 and C1 in Fig. 3. Diodes D1A and D1B are due to the base emitter PN junctions of the transistors. Capacitors C1A and C1B are the associated capacitors of the base emitter junctions of the two devices. Capacitors C2A and C2B are capacitors associated with the Collector to P Substrate of the IC. Since devices QA and QB are of identical geometry and in close proximity, capacitors C2A and B and capacitors C1A and B have identical C-V or capacitance versus applied voltage curves. This is important since the junction capacitance varies strongly with applied voltage. Fig. 3 shows the differential single shot which uses this differential capacitor as shown in Fig. 1 and also in Fig. 2. The capacitor connects between connectors C0 and C1. The ARFN terminal has a current source bias voltage on it, and the terminals Y1 and Y2 have differential logic outputs on them. Y1 may be considered to be the true logic input, and Y2 is the complement. The connectors 10 and 20 are the outputs of the Fig. 3 circuit. The polarity of connection of the capacitor to connectors C0 and C1 makes no difference due to the symmetry of the differential capacitor. The inputs to the...