Browse Prior Art Database

Bus Data Transfer Controls for Personal Computers

IP.com Disclosure Number: IPCOM000040768D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 44K

Publishing Venue

IBM

Related People

Dean, ME: AUTHOR [+7]

Abstract

A technique is described whereby efficient data transfer controls are provided across an address bus of a personal computer (PC), with a minimum access overhead to the memory of the system. A new set of transfer controls to the channel for personal computers provides a more compact presentation of data as well as reduces the complexity and cost at the planer board. The five new controls are as follows: 1. Potential 0 wait state operation of memory 2. Default 1 wait state operation of input/output (I/O) 3. Expanded status reporting to feature systems 4. Support of advanced co-processor/subsystem designs 5. Simple circuitry for one additional wait state for memory and I/O The address bus of the PC is re-powered and presented to the channel with minimum delay.

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Bus Data Transfer Controls for Personal Computers

A technique is described whereby efficient data transfer controls are provided across an address bus of a personal computer (PC), with a minimum access overhead to the memory of the system. A new set of transfer controls to the channel for personal computers provides a more compact presentation of data as well as reduces the complexity and cost at the planer board. The five new controls are as follows: 1. Potential 0 wait state operation of memory

2. Default 1 wait state operation of input/output

(I/O)

3. Expanded status reporting to feature systems

4. Support of advanced co-processor/subsystem designs

5. Simple circuitry for one additional wait state for

memory and I/O The address bus of the PC is re-powered and presented to the channel with minimum delay. This enables feature designs to begin address decoding earlier in the cycle and will only latch the results of the decode and only those low-order bits needed to select multiple functions within an address space. Since the address bus is unlatched, a one hundred-nanosecond address set-up time advantage is provided and offers a zero wait state memory operation. It is, therefore, evident that a PC operation at 8 MHz could perform as fast as a 10 MHz PC without the new transfer controls, since they operate memory at zero wait states on the I/O channel. The new address bus is valid until the status bus becomes valid. Also, a new signal is provided to assist the operation with address spaces greater than 16 megabytes. All processo...