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Multi-Plate Storage Capacitor for DRAM

IP.com Disclosure Number: IPCOM000040772D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 38K

Publishing Venue

IBM

Related People

Ning, TH: AUTHOR

Abstract

A multiple plate storage capacitor can be constructed for a dynamic random-access memory (DRAM) cell resulting in less sensitivity to soft error effects and having higher speeds. (Image Omitted) A fabrication process for a multi-plate trench capacitor cell in a p-epitaxy, n-well CMOS wafer is shown in Figs. 1-4. Assuming n-well 1 on a p-epitaxy layer 2 of p+ substrate 3, pad oxide 4 is grown and nitride 5 and oxide 6 are deposited, as shown in Fig. 1. Trench capacitor region 7 is patterned and etched to the n-well surface. In Fig. 2, oxide 6 is used as a mask to selectively remove some of the silicon by reactive ion etching (RIE). Polysilicon layer 8 is deposited and selectively etched by RIE to leave sidewalls 9. If necessary, a thin oxide can be grown prior to polysilicon deposition to serve as a stop during etching.

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Multi-Plate Storage Capacitor for DRAM

A multiple plate storage capacitor can be constructed for a dynamic random- access memory (DRAM) cell resulting in less sensitivity to soft error effects and having higher speeds.

(Image Omitted)

A fabrication process for a multi-plate trench capacitor cell in a p-epitaxy, n-well CMOS wafer is shown in Figs. 1-4. Assuming n-well 1 on a p-epitaxy layer 2 of p+ substrate 3, pad oxide 4 is grown and nitride 5 and oxide 6 are deposited, as shown in Fig. 1. Trench capacitor region 7 is patterned and etched to the n-well surface. In Fig. 2, oxide 6 is used as a mask to selectively remove some of the silicon by reactive ion etching (RIE). Polysilicon layer 8 is deposited and selectively etched by RIE to leave sidewalls 9. If necessary, a thin oxide can be grown prior to polysilicon deposition to serve as a stop during etching. An oxide layer is deposited and selectively etched by RIE to form sidewalls 10 abutting the polysilicon sidewalls. Polysilicon is then deposited and etched back by RIE or chemical-mechanical polishing to a planar surface.

(Image Omitted)

With oxide 6 and 10 as a mask, RIE is used to selectively remove polysilicon and silicon to form trenches 12 the desired depth, as in Fig. 3. The oxide is removed and a thin oxide layer 13 or optional nitride layer are deposited on the silicon surfaces. In Fig. 4, trenches 12 are filled with polysilicon 14 and etched back to form the storage electrode. The substrate serves as...