Browse Prior Art Database

Self-Time Pulsed Wordline

IP.com Disclosure Number: IPCOM000040774D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Chappell, BA: AUTHOR [+3]

Abstract

For fast cycle time and low power in a static random-access memory, a pulsed wordline is needed. Previous approaches, as shown in Fig. 1, involved more complicated wiring to global signals and were too slow [*]. For high performance applications, an improved circuit is shown in Fig. 2 which uses the wordline (WL) to reset the NOR decoder node directly. The circuit is tuned to the proper time by varying the ratio of transistors 1 and 2, 3 and 4, 5 and 6. Reference * B. A. Chappell, P. W. Cook, R. L. Franch, P. F. Greier, S. P. Klepner, F. S. Lai, R. A. Lipa, R. J. Perry, W. F. Pokornoy and M. A. Roberge, "A 15ns CMOS 64K RAM," IEEE Journal of Solid-StateCircuits SC-21, 5, 704-712 (October 1986).

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Self-Time Pulsed Wordline

For fast cycle time and low power in a static random-access memory, a pulsed wordline is needed. Previous approaches, as shown in Fig. 1, involved more complicated wiring to global signals and were too slow [*]. For high performance applications, an improved circuit is shown in Fig. 2 which uses the wordline (WL) to reset the NOR decoder node directly. The circuit is tuned to the proper time by varying the ratio of transistors 1 and 2, 3 and 4, 5 and 6. Reference * B. A. Chappell, P. W. Cook, R. L. Franch, P. F.

Greier, S. P. Klepner, F. S. Lai, R. A. Lipa, R. J. Perry, W.

F. Pokornoy and M. A. Roberge, "A 15ns CMOS 64K RAM,"

IEEE Journal of Solid-StateCircuits SC-21, 5, 704-712

(October 1986).

1

Page 2 of 2

2

[This page contains 4 pictures or other non-text objects]