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Test Structures for Transistor Chains with Isolation Integrity

IP.com Disclosure Number: IPCOM000040841D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Hershberger, DB: AUTHOR

Abstract

Disclosed is a method for early defect monitoring and diagnosi of semiconductor devices during the manufacturing process. This paper suggests the interconnection of polysilicon (poly) lines to form mazes at the masterslice level.

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Test Structures for Transistor Chains with Isolation Integrity

Disclosed is a method for early defect monitoring and diagnosi of semiconductor devices during the manufacturing process. This paper suggests the interconnection of polysilicon (poly) lines to form mazes at the masterslice level.

In conventional processing of semiconductor devices masterslic defect monitoring structures are tested in personalization areas after wiring with metals at different levels. The underly- ing masterslice topology has limited utility since all contacts to devices are made with one of the metal levels.

The procedure proposed herein uses poly emitter and poly base technology which makes it possible to contact the devices without affecting the personalization structure. A transistor chain established under the metal personalization structure has emitters and bases wired in parallel with the collector contacted through the subcollector. The technology provides for connecting adjacent subcollector beds separated by trenches to test pads for isolation integrity measurements.

The test structure may be fabricated by poly emitter contact and poly base contact to each adjacent subcollector isolation bed. A blanket reach-through is necessary to compensate for the base implant and the base poly drive-in. This allows the poly base and poly emitter to contact the subcollector.

When testing the structure it is necessary to distinguish shorts and leakage problems. The base must be forward bias...