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Process and Mask Structure for Submicrometer-Wide Polysilicon or Polycide Emitters

IP.com Disclosure Number: IPCOM000040868D
Original Publication Date: 1987-Feb-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 14K

Publishing Venue

IBM

Related People

Lechaton, JS: AUTHOR [+4]

Abstract

A method has been proposed to make very narrow emitters required for high performance bipolar transistors. This article suggests merging processing techniques for the polycide emitter transistor and sidewall image transfer to achieve the desired structure.

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Process and Mask Structure for Submicrometer-Wide Polysilicon or Polycide Emitters

A method has been proposed to make very narrow emitters required for high performance bipolar transistors. This article suggests merging processing techniques for the polycide emitter transistor and sidewall image transfer to achieve the desired structure.

In bipolar transistors the emitter current flows near the emitter periphery due to the voltage drop along the base-emitter junction. Since an increase in the emitter periphery will increase the current-carrying capacity, it is desirable to make

(Image Omitted)

the ratio of periphery to emitter area as large as possible. This is achieved by making the emitter long and narrow -- submi- cron-wide.

Disclosed herein is a process for making a submicron-wide mask structure using sidewall image transfer technique. The mask structure is then used to etch N+ polysilicon or polycide patterns which form the emitter and provide contacts for first level metal wiring.

Conventional processing is used up to and including intrinsic base implant and base drive-in to get the supporting structure of Fig. 1 with the N- collector 1, base 2 and recessed oxide isolation (ROI) or trench 3. A layer of N+ doped polysilicon 4 topped with the desired polycide 5 is deposited. An insulating film, such as chemical vapor deposition (CVD) oxide 6, is next laid down to act as a barrier during emitter drive-in and as an insulator between the polycide and first metal.

A layer of photoresist (PR) 7 is deposited and baked and covered with a thin layer of sputtered silicon 8. A multilevel resist (MLR) mandrel 9 is formed with vertical sidewall. A low temperature CVD oxide is deposited and etched back to the sputtere silicon 8 to form an oxide sidewall 10. The oxide thickness is chosen depending upon the desired width of the sidewall and hence the emitter width.

The mandrel is removed by ashing in O2 with...