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Improved Thermal Package for VLSI Chips

IP.com Disclosure Number: IPCOM000040949D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Braen, RC: AUTHOR

Abstract

A VLSI package 2 featuring direct heatsink 4 attachment to the back side of a VLSI chip 6 is shown. The chip 6 is electrically connected to a substrate 7 using solder balls 8 or other conventional direct chip circuit attachment. The direct mounted heatsink 4 gives an improved thermal path from the chip 6 to the cooling medium. This results in a lower device junction temperature, Tj, which, in turn, results in faster performance and improved reliability for CMOS technology.

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Improved Thermal Package for VLSI Chips

A VLSI package 2 featuring direct heatsink 4 attachment to the back side of a VLSI chip 6 is shown. The chip 6 is electrically connected to a substrate 7 using solder balls 8 or other conventional direct chip circuit attachment. The direct mounted heatsink 4 gives an improved thermal path from the chip 6 to the cooling medium. This results in a lower device junction temperature, Tj, which, in turn, results in faster performance and improved reliability for CMOS technology.

The package 2 includes a flexible membrane 10 such as polyimide for environmental isolation and a protective enclosure 11 which allows unrestricted cooling medium flow across the heatsink 4 and protects the chip 6 from handling and accidental damage.

The concept can be applied to individual chips in a multichip package 2 (shown in the drawing) or a single chip package. The heatsink size and form factor is designed to meet the space and cooling medium requirements. For any given set of physical conditions, the direct attached heatsink has superior performance.

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Disclosed anonymously

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