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Binary Shift Counter

IP.com Disclosure Number: IPCOM000040968D
Original Publication Date: 1987-Apr-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Lewis, SD: AUTHOR

Abstract

An LSSD logic implementation is used to count to a few pre-determined values with a minimum amount of circuitry. This counter can be both incremented and decremented as long as the count remains between the initial value and a maximum value. Incrementing and decrementing involve a simple shifting operation and, hence, a minimum amount of logic. Particular counts can be identified by 'AND'ing the desired bit pattern together.

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Binary Shift Counter

An LSSD logic implementation is used to count to a few pre-determined values with a minimum amount of circuitry. This counter can be both incremented and decremented as long as the count remains between the initial value and a maximum value. Incrementing and decrementing involve a simple shifting operation and, hence, a minimum amount of logic. Particular counts can be identified by 'AND'ing the desired bit pattern together.

If the desired function involves only incrementing to a desired value and then resetting the counter in the Figure, the 'D' input will be an '0' which results in blocks 100, 101, 102, 103, 104 and 303 being simplified. The 'I' input can also be removed everywhere except the input to block 105. This results in even further savings of logic.

Blocks 104, 204 and 304 are used to maintain odd parity in the entire unit. They may be eliminated if the shifter does not require any parity checking. To handle a larger range of counts, blocks 102 and 202 are duplicated.

Operation is started by initializing the counter. All SRLs are Reset except the 'n'th one (block 203). This one is Set. This will load a pattern of the form '000...001'b. By decoding the bit pattern in the SRLs, it can be determined what the count is. For instance, a decode of '0001' would imply a count of 0 in a 4 bit counter.

When the count is incremented, all of the data bits are shifted once to the right, while bit 0 (block 200) is loaded with the XOR of itself an...