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Method to Reduce Soft Errors in Control Stores by Use of Self Checking

IP.com Disclosure Number: IPCOM000041003D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Wade, WT: AUTHOR

Abstract

To provide error detection and correction, control stores are divided into two halves, each with its own error correcting code (ECC) hardware address counter and controls. Control programs are written such that each half of the control store is used by the system every other cycle. During the off cycle in each half, a separate address counter checks each address (one per off-cycle) to detect and correct an error using ECC. Thus, soft errors are nearly completely eliminated and hard errors are detected by a recheck and further use of a bad address may be avoided.

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Method to Reduce Soft Errors in Control Stores by Use of Self Checking

To provide error detection and correction, control stores are divided into two halves, each with its own error correcting code (ECC) hardware address counter and controls. Control programs are written such that each half of the control store is used by the system every other cycle. During the off cycle in each half, a separate address counter checks each address (one per off-cycle) to detect and correct an error using ECC. Thus, soft errors are nearly completely eliminated and hard errors are detected by a recheck and further use of a bad address may be avoided.

Use (reading or writing) and checking proceeds on alternate cycles within each half of the divided control store until an error is found. At this point, the data in the failing address is corrected and rechecked in subsequent off-cycles. If the error is soft, the process of sequentially checking each address continues. If the error cannot be corrected, a hard fail is identified and appropriate action is taken to avoid reuse of the bad address. Thus, several cycles (usually three) are used for error correction on the occasion of detection of an error.

Note that while error checking is performed sequentially through control store addresses on alternate cycles, use is being made of control store addresses in an unknown sequence on the other cycles. It is therefore possible to lose a bit in an address that gets used (read) before it gets r...