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CMOS Memory Sorted for Yield Versus Reliability

IP.com Disclosure Number: IPCOM000041004D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Gray, KS: AUTHOR [+2]

Abstract

A dynamic random access memory (DRAM) chip is designed and equipped to be operated with or without bootstrapped word lines. While the bootstrapped (higher) voltage level on the word lines provides higher output signal and thus high yield, the higher voltage level reduces reliability. Thus, a first sort of those chips which provide acceptable output signal without bootstrapped word lines provides chips for high reliability applications. Word line bootstrapping is enabled on remaining chips by blowing a fuse or changing D.C. voltage level on one pad. Chips thus enabled for word line bootstrapping are then tested for use in applications not requiring the higher reliability.

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CMOS Memory Sorted for Yield Versus Reliability

A dynamic random access memory (DRAM) chip is designed and equipped to be operated with or without bootstrapped word lines. While the bootstrapped (higher) voltage level on the word lines provides higher output signal and thus high yield, the higher voltage level reduces reliability. Thus, a first sort of those chips which provide acceptable output signal without bootstrapped word lines provides chips for high reliability applications. Word line bootstrapping is enabled on remaining chips by blowing a fuse or changing D.C. voltage level on one pad. Chips thus enabled for word line bootstrapping are then tested for use in applications not requiring the higher reliability.

The figure is a schematic showing circuitry added to a standard CMOS DRAM to provide selection of word line operation with or without bootstrapping. A fuse or programming pad voltage is brought to logic gate 2 on input A when bootstrapped operation is desired. If the bootstrapped portion of the word line driver 6 is selected, unbootstrapped word line driver 4 is isolated from the load via a voltage pulse from logic gate 2 through line B before bootstrapping. Transistor T is to keep bootstrap capaci- tor C isolated from the load when the bootstrapped portion of the word line driver 6 is not selected.

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Disclosed anonymously

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