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A Sidewall Image Definition Technique for Producing Extremely Fine Semiconductor Chip Features

IP.com Disclosure Number: IPCOM000041005D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Abrams, AD: AUTHOR [+2]

Abstract

A simple process is reported for defining a mask which will produce extremely fine image sizes and line pitches in a semiconductor wafer utilizing current photolithographic tools and techniques.

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A Sidewall Image Definition Technique for Producing Extremely Fine Semiconductor Chip Features

A simple process is reported for defining a mask which will produce extremely fine image sizes and line pitches in a semiconductor wafer utilizing current photolithographic tools and techniques.

To demonstrate the process, a simplified embodiment of resist on SiO2 is described. An imaging resist is applied to the final image layer (SiO2), exposed and developed as shown in Fig. 1.

The sidewalls of the exposed resist, shown in Fig. 2, are hardened utilizing a CF4 + H2 reactive ion etch (RIE) or straight plasma mode. The length of time used to etch determines the amount of resist hardened which is a function of mask width required. Depending on the material used for the image layer, the hardening etch conditions can be adjusted to prevent etching of the final image.

The non-hardened resist is removed, as shown in Fig. 3, leaving the hardened sidewall image resist which is used as a mask to etch the final image layer. The hardened mask material is impervious to a wide range of reactive ion etches in the fluorine and chlorine based chemistries. The mask can be removed in a diluted BHF. Fig. 4 shows the final image produced in SiO2.

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