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Shorts and Continuity Testing using an MISR and Signature Analysis

IP.com Disclosure Number: IPCOM000041015D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Ekquist, K: AUTHOR [+3]

Abstract

This article describes the use of a Multiple Input Shift Reg- ister ("MISR") to test for shorts, continuity and interface faults between a Source and Sink Card. A test pattern is clocked from a source Chip/Card to a Sink Chip/Card; each time the pattern is clocked, a signature is generated in the "MISR". The signature in the illustrated embodiment is "p" bits long, where "p" = 20. A composite "p" bit signature represents a plurality and variety of test patterns.

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Shorts and Continuity Testing using an MISR and Signature Analysis

This article describes the use of a Multiple Input Shift Reg- ister ("MISR") to test for shorts, continuity and interface faults between a Source and Sink Card. A test pattern is clocked from a source Chip/Card to a Sink Chip/Card; each time the pattern is clocked, a signature is generated in the "MISR". The signature in the illustrated embodiment is "p" bits long, where "p" = 20. A composite "p" bit signature represents a plurality and variety of test patterns.

Conventionally, interconnections from source to sink between chips/cards must be "mapped" into "Compare Masks"; i.e., D1 to R1, D2 to R2, etc. Results (Sink) must be stored and/or compared for each test pattern. For a "Walking 1" pattern, there are (n + m)2 bits of temporary memory required for the "Compare Masks", and up to N + m bits of temporary memory required to save test results
i.e., if (n + m) = 1 X 103 interconnections, than the masks = require 106 bits of memory.

Referring to the drawing, the following sequence is employed: 1. Test pattern employed is "walking 1" through all intercon- nected drivers/receivers/conductors. 2. Clock test pattern applied to chip/card source and chip/card ink. 3. Generate the "MISR" signature. 4. Repeat steps 2-3 until all interconnects are tested. 5. At completion of test, read and compare "p" bit signature and "p" bit mask. Signature and Mask = 20 bits each.

The advantages of the above described imp...