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Browse Prior Art Database

CMOS On-Chip VDD Lock-Out Pulse

IP.com Disclosure Number: IPCOM000041019D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Dutta, S: AUTHOR

Abstract

A circuit is disclosed that generates an on-chip signal at the application of the supply voltage, and at the same time prevents the pulse signal from recurring once the operation has been established. Fig. 1 is a circuit schematic, having letters identifying various nodes. Fig. 2 is a diagram of voltage waveforms, identified by letters corresponding to the nodes in Fig. 1 where the waveforms are taken.

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CMOS On-Chip VDD Lock-Out Pulse

A circuit is disclosed that generates an on-chip signal at the application of the supply voltage, and at the same time prevents the pulse signal from recurring once the operation has been established. Fig. 1 is a circuit schematic, having letters identifying various nodes. Fig. 2 is a diagram of voltage waveforms, identified by letters corresponding to the nodes in Fig. 1 where the waveforms are taken.

The operation is as follows. As the supply voltage VDD turns on, node A voltage begins climbing according to the RC time constant. When VDD reaches the threshold voltage of device N1, N1 is turned on. Node B is pulled down to VSS, (logic "0"). Simultaneously, node C voltage starts to rise along with the VDD voltage, since device T2 is turned on. Since the gate of P1 is tied to node B, device P1 acts like a current mirror of P2. As soon as the node B voltage rises to the threshold voltage of the N2 device, the N2 device is turned on, and node C is pulled down to the VSS level. This causes the P3 device to turn on. Conse- quently pulse, and thereafter remains low.

The advantages of this curcuit arrangement are as follows. First, no external system power-up reset is necessary. Second, since few devices are used, the circuit can be easily incorporated into any CMOS chip. Finally, all of the devices, except for the N2 device, are high impedance CMOS devices. Consequently, very li tle DC current is involved.

Disclosed anonymously

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