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Compare Status Accumulator

IP.com Disclosure Number: IPCOM000041020D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Schoenike, RL: AUTHOR [+2]

Abstract

Compare operations (comparing the value of two words) are fre- quently performed in processors. The compares are performed within the ALU of the processor on words whose width is equal to the width of the data flow of the machine. When the compare must be performed on data values whose width is greater than the width of the data flow of the machine, multiple compares must be performed and the output of the compares tested to ensure that all the compares were valid. For example, for a 32 bit compare of two words in a machine with a 16 bit data flow, the lower halves would be compared first and then the upper halves. If both compares were valid, then the words were equal in value.

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Compare Status Accumulator

Compare operations (comparing the value of two words) are fre- quently performed in processors. The compares are performed within the ALU of the processor on words whose width is equal to the width of the data flow of the machine. When the compare must be performed on data values whose width is greater than the width of the data flow of the machine, multiple compares must be performed and the output of the compares tested to ensure that all the compares were valid. For example, for a 32 bit compare of two words in a machine with a 16 bit data flow, the lower halves would be compared first and then the upper halves. If both compares were valid, then the words were equal in value.

This type of operation was required on the processor with its 16 bit data flow and was implemented such that any word width multiple of 16 bits could be compared. The first compare (com- paring the low 16 bits of both words) is done and its equal flag loaded into a hardware status register bit. The next microcycle of the next 16 bits of each word are compared and accumulated with the first compare flag held in the hardware status register bit. The accumulation is done by issuing, under microcode control, the control register decode equal double which logically "ands" the result of the previous compare with the results of the current compare. The accumulation can go on for any multiple of 16 bits. The result held in the hardware status register bit at the end of...