Browse Prior Art Database

Buried Contact Formation

IP.com Disclosure Number: IPCOM000041042D
Original Publication Date: 1987-May-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Chao, H: AUTHOR [+6]

Abstract

This article relates generally to integrated circuit construct and, more particularly, to fabrication of buried contacts for a static random access memory (SRAM).

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Buried Contact Formation

This article relates generally to integrated circuit construct and, more particularly, to fabrication of buried contacts for a static random access memory (SRAM).

Less damage occurs to the gate oxide in buried contact formation by avoiding photoresist removal from the entire gate area and eliminating reactive ion etching of the gate.

In Fig. 1a, gate area 1 of either n+ or p+ silicon substrate 2 is defined in oxide layer 3 through an opening in n+ polysilicon layer 4. Spacer 5 is formed at the gate edges. Thereafter, in Fi 1b, photoresist 6 is developed to form the buried contact site, and titanium 7 and amorphous silicon 8 are evap- orated over the exposed spacer. Photoresist 6 is then removed and salicide is formed on the gate and source/drain.

During processing, the titanium and amorphous silicon, which can be co- evaporated, should be large enough to make a good contact. The n+ polysilicon gate can be contacted to both n+ and p+ source/drain, useful particularly in CMOS processes. Alterna- tively,a titanium nitride film may be used to make the connec- tion between the polysilicon and n+ or p+ diffusion to eliminate interdiffusion problems. Either method can be carried out prior to normal titanium-silicon dioxide formation.

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