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A Novel Method for Planarization Semiconductor Industry Wafers by the Use of a Dot-Pattern Block-Out Mask

IP.com Disclosure Number: IPCOM000041129D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Collini, GJ: AUTHOR [+3]

Abstract

Some technologies require that a semiconductor wafer structure be made planar at various stages of its build. This article describes a four-step process for changing a severe topography, multi-level wafer surface to a planar polymeric surface suitable for subsequent lithographic or planar etch-back processing.

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A Novel Method for Planarization Semiconductor Industry Wafers by the Use of a Dot-Pattern Block-Out Mask

Some technologies require that a semiconductor wafer structure be made planar at various stages of its build. This article describes a four-step process for changing a severe topography, multi-level wafer surface to a planar polymeric surface suitable for subsequent lithographic or planar etch-back processing.

Spun on, photoresist (P/R) planarizing layers, are never completely planar due to the underlying geometry of substrate topographic features, as illustrated in the cross-section drawing in Fig. 1 showing a layer 10 of photoresist on substrate
11. By employing a specially designed block-out mask in the process described below, excess P/R material can be removed in direct proportion to the excess P/R thickness existing over any feature of that geometry.

The process includes the following four steps:

1) The wafer/substrate is coated with a film of a positive- working P/R and then partially processed by being given a "soft bake".

2) A patterned lithographic mask is aligned over the coated wafer and exposed. The mask employs a "polka- dot" pattern of "windows" (non-plated areas) whose density is determined in proportion to the excess P/R present on the wafer (as compared to a planar surface). The pattern used is selected after study of the parti cular substrate topology and an evaluation of the P/R thickness following coating.

3) The exposed substrate is deve...