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Clock Frequency Multiplication by Powers of Two

IP.com Disclosure Number: IPCOM000041141D
Original Publication Date: 1987-Sep-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

IBM

Related People

DasGupta, S: AUTHOR

Abstract

During the design of a logic system, particularly when existing pieces of logic, designed in different groups, are integrated to build a system, there is a need, sometimes, for a clock frequency that is higher than the available clock frequency. The easy, though not always acceptable, solution is to add a separate oscillator to provide the additional clocks. Unfortunately, the problem is that separate oscillators do not necessarily run together in synchronism, resulting in metastability when signals from one clock system have to be stored in latches controlled by another clock system. Metastability, in turn, requires care in handling and additional hardware to avoid it. The drawing shows a frequency doubler circuit and a way to cascade several of such circuits to produce frequency multiplication by powers of two.

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Clock Frequency Multiplication by Powers of Two

During the design of a logic system, particularly when existing pieces of logic, designed in different groups, are integrated to build a system, there is a need, sometimes, for a clock frequency that is higher than the available clock frequency. The easy, though not always acceptable, solution is to add a separate oscillator to provide the additional clocks. Unfortunately, the problem is that separate oscillators do not necessarily run together in synchronism, resulting in metastability when signals from one clock system have to be stored in latches controlled by another clock system. Metastability, in turn, requires care in handling and additional hardware to avoid it. The drawing shows a frequency doubler circuit and a way to cascade several of such circuits to produce frequency multiplication by powers of two.

Fig. 1 shows the basic frequency doubling network or doubler 10. It includes a 2-input Exclusive-OR circuit 11. One input of 11 is fed by the clock frequency or signal that is to be doubled. The other input to 11 comes from a delay network 12 which is also fed by the same clock input. The resultant clock out signal is exactly twice the frequency of the clock in input (see Fig. 2). Note that the width of the clock pulse at the output of the Exclusive-OR (that is, how long it is "up" and how long it is "down") is determined by the amount of delay in the delay network. This, however, does not affect the freque...