Browse Prior Art Database

Borderless Diffusion Contact Process for Array Structures

IP.com Disclosure Number: IPCOM000041149D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Davis, A: AUTHOR

Abstract

A process for making a contact which is insensitive to misalignment is described. A large contact hole may be used without increasing area occupied by a device.

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Borderless Diffusion Contact Process for Array Structures

A process for making a contact which is insensitive to misalignment is described. A large contact hole may be used without increasing area occupied by a device.

This process begins at a point in field effect transistor (FET) array construction depicted in Fig. 1, wherein there is a recessed oxide region 2, source diffusion 4, and drain diffusion 6 built into silicon substrate 8. Polysilicon (or silicide) 10 is deposited on thin gate dielectric 12, coated with oxide layer 14, and photoetched to form a gate electrode. A conformal coating of oxide is deposited and reactive ion etched (RIE'd) to leave sidewall oxide regions 16.

This diffusion contact process begins in Fig. 2 by applying a conformal thin layer of silicon nitride 18 and polysilicon etch stop layer 20, then applying a thick layer of a reflowable glass 22, e.g., boron phosphorous silicon glass (BPSG). Photoresist 24 is applied next and opening C is defined in photoresist 24 by standard photo processing. Note that the contact hole opening C in the photoresist 24 may be oversize and or misaligned relative to the size and position of drain diffusion 4. RIE is used to selectively etch through BPSG layer 22, thus permitting complete removal of layer 22 in all exposed areas because of the etch stop layer 20.

To arrive at the cross-section shown in Fig. 3, photoresist 24 is stripped, and BPSG 22 is reflowed. The oxidizing environment of the reflow proces...