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Enhanced Circuit Performance for a 1.0 Micron Cmos Process

IP.com Disclosure Number: IPCOM000041162D
Original Publication Date: 1987-Oct-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Barber, J: AUTHOR [+2]

Abstract

An increase in the circuit performance of semiconductor devices can be achieved by the reduction of the sheet resistance of the polysilicon interconnection lines lying over the field oxide region. The use of composite materials such as tungsten silicide - polysilicon (polysilicide) will result in a significantly lower sheet resistance. However, numerous additional problems, such as delamination, are inherent to this approach. The selective substitution of titanium for the polysilicon can reduce the sheet resistance of the polysilicon interconnection lines. This substitution can be accomplished with known processes for selective removal of the polysilicon lines and subsequent deposition of titanium.

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Enhanced Circuit Performance for a 1.0 Micron Cmos Process

An increase in the circuit performance of semiconductor devices can be achieved by the reduction of the sheet resistance of the polysilicon interconnection lines lying over the field oxide region. The use of composite materials such as tungsten silicide - polysilicon (polysilicide) will result in a significantly lower sheet resistance. However, numerous additional problems, such as delamination, are inherent to this approach. The selective substitution of titanium for the polysilicon can reduce the sheet resistance of the polysilicon interconnection lines. This substitution can be accomplished with known processes for selective removal of the polysilicon lines and subsequent deposition of titanium.

Disclosed anonymously.

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