Browse Prior Art Database

BI-FET Receiver

IP.com Disclosure Number: IPCOM000041179D
Original Publication Date: 1987-Nov-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

Both FET and BIPOLAR elements are used in a receiver design which consumes low power and provides high performance.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 1

BI-FET Receiver

Both FET and BIPOLAR elements are used in a receiver design which consumes low power and provides high performance.

When input Vin rises from a logical 0 to a 1, node A is discharged through device 6 when Vin reaches the threshold voltage of device 2 plus the base- emitter voltage of device 6 (Vth(2) + Vbe(6) ). Node B then comes high. When device 5 is on, the switch point of the input is shifted down to the value of the threshold voltage ,Vth(2), of device 2. As the input Vin falls from a 1 to a 0, node A begins to charge through device 1. Nodes A and C, however, are held low through devices 2 and 5 until Vin falls through the threshold voltage of device 2. Device 2 is large to keep the drop small, and reduce shifts in threshold voltage. When Vin drops below the Vth(2), node A charges quickly to VDD and node B back to ground.

Disclosed anonymously.

1