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Exponent Equate And Magnitude Comparison of Floating Point Numbers

IP.com Disclosure Number: IPCOM000041209D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Wyatt, VD: AUTHOR

Abstract

A technique is described whereby computer logic architecture is provided to reduce the time required in the determination of equal exponent of operands and the magnitude of the exponent.

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Exponent Equate And Magnitude Comparison of Floating Point Numbers

A technique is described whereby computer logic architecture is provided to reduce the time required in the determination of equal exponent of operands and the magnitude of the exponent.

Computer floating point addition and subtraction typically requires that the operands have exponents of equal magnitude. The right shifting of the fraction of the smaller number and the incrementing of the exponent occur in a microcode loop. The smaller of two numbers must be determined through comparison operations. Previous floating point processors required several microcycles to select only the exponent parts of the operands and determined which operand should be operated on to equate the exponents in preparation for floating point addition or subtraction. The concept described herein reduces the time required for this determination.

Looping controls first equate two floating point numbers as to the magnitude of the exponents. After determining the larger of the two numbers, from the magnitude microinstruction, the larger number is placed in a multiply/quotient (M/Q) register and the smaller number is placed in one of two registers used for floating point conversion. The two numbers are then concatenated. Hardware controls, in conjunction with the microword loop controls, shift the registers right one hexadecimal character and decrements the exponent of the M/Q register each cycle until the exponent in the M/Q...