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Sidewall Diffused Node Array Device With Deep Buried Implant

IP.com Disclosure Number: IPCOM000041211D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Kenney, DM: AUTHOR [+2]

Abstract

In a dynamic memory cell having a node storage trench, relatively high punch-through voltage is attained by implanting a p-type region at a level slightly deeper than an N+ bitline diffusion. In addition, a sidewall diffused p-type region is formed in the node storage trench below the level of the implanted region. Thus, a storage node structure is formed which, by permitting higher voltage on a standard capacitance, provides high signal to a sense amplifier.

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Sidewall Diffused Node Array Device With Deep Buried Implant

In a dynamic memory cell having a node storage trench, relatively high punch-through voltage is attained by implanting a p-type region at a level slightly deeper than an N+ bitline diffusion. In addition, a sidewall diffused p-type region is formed in the node storage trench below the level of the implanted region. Thus, a storage node structure is formed which, by permitting higher voltage on a standard capacitance, provides high signal to a sense amplifier.

Referring to the figure, deep p-type ion implant 2 is formed in silicon substrate 4 at a depth slightly below the depth of Nbitline diffusion 6. In addition, a p-type diffusion 8 is created below implanted region 2 and in contact with the lower portion of diffused n+ storage node 10, as shown. Remaining structure shown in the figure is standard storage dielectric 12, polysilicon trench fill 14, and word line 16 disposed above shallow tailoring implant 18.

Disclosed anonymously.

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