Browse Prior Art Database

Speed Detector Circuit

IP.com Disclosure Number: IPCOM000041213D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Horowitz, PN: AUTHOR [+3]

Abstract

A circuit is described which detects signals from an off-chip-driver (OCD) comparison circuit for relative process speed and converts these signals to a stable digital signal for use in an OCD performance control circuit.

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Speed Detector Circuit

A circuit is described which detects signals from an off-chip-driver (OCD) comparison circuit for relative process speed and converts these signals to a stable digital signal for use in an OCD performance control circuit.

Referring to Fig. 1, signals IS (from a device insensitive to process variation) and S (from a device sensitive to process variation) come from the comparison circuit with one of the signals going from +Vdd to 0 Volts faster than the other. In the case shown in Fig. 1, the signal S is faster than the signal IS. The latch comprised of transistors T2 and T4 in the circuit shown in Fig. 2 detects the faster signal S, inhibits the slow signal IS, and latches the faster process output FP to a 1 and the slower process output SP to a 0 through inverters In4 and In2, respectively. P-type transistors T6 and T8 are pull-ups used to latch nodes A and B. Grounded gate transistors T10 and T12 are small devices used to reset nodes A and B to Vdd when signals IS and S rise.

The output signals FP and SP can be used to define the limits of performance of an OCD within a range suited to a shift in speed (from nominal) caused by process variations.

Disclosed anonymously.

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