Browse Prior Art Database

Circuit for Connecting System Clock Or Test Clock to Logic Circuits

IP.com Disclosure Number: IPCOM000041230D
Original Publication Date: 1987-Dec-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 12K

Publishing Venue

IBM

Related People

Askin, HO: AUTHOR [+2]

Abstract

The system clock and the logic circuits of a data processor are interconnected through a circuit that permits a different clock to be substituted in order to test the logic circuits. The logic circuits require both the true and complement clock phases, and the interconnecting circuit includes a differential amplifier stage followed by an emitter follower stage for each phase of the clock, as is conventional. Each phase of the test clock is coupled to the interconnecting circuit by means of a transistor that has its base terminal connected to receive the test clock signal and its emitter terminal connected in the signal path.

This text was extracted from a PDF file.
This is the abbreviated version, containing approximately 77% of the total text.

Page 1 of 1

Circuit for Connecting System Clock Or Test Clock to Logic Circuits

The system clock and the logic circuits of a data processor are interconnected through a circuit that permits a different clock to be substituted in order to test the logic circuits. The logic circuits require both the true and complement clock phases, and the interconnecting circuit includes a differential amplifier stage followed by an emitter follower stage for each phase of the clock, as is conventional. Each phase of the test clock is coupled to the interconnecting circuit by means of a transistor that has its base terminal connected to receive the test clock signal and its emitter terminal connected in the signal path.

In an improved circuit, the test clock signal coupling transistor has its emitter terminal connected to the output node of the emitter follower stage to form a differential amplifier pair with the emitter follower transistor. This configuration avoids the conventional connection of the test clock signal coupling transistor as a differential pair with one of the differential amplifier transistors and thereby removes the capacitance at the collector terminal of this transistor from the path of the system clock signal.

In the drawing, transistors 2 and 3 and resistors 4-6 form the differential amplifier and receive normal clock inputs A and Not A. Transistors 7 and 8 produce the clock outputs C and Not C. Transistors 9 and 10 receive the alternate clock inputs B and Not B. Input...