Browse Prior Art Database

Railless Bipolar Process

IP.com Disclosure Number: IPCOM000041287D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 49K

Publishing Venue

IBM

Related People

Hu, CC: AUTHOR [+2]

Abstract

In the current process, the extrinsic base polysilicon is defined by reactive ion etching (RIE). Polysilicon rails are left behind near the steps especially the back of the "bird's head" of recessed oxide isolation (ROI). Extensive overetch is required during RIE to remove these rails. The overetch also removes the insulation layer, such as silicon dioxide (SiO2), due to the finite etch rate ratio during RIE. As a result, the final topology is difficult to predict. The process starts by first forming the usual structure of a substrate 10, an epitaxial layer 14 over substrate 10 and a subcollector layer 12. Regions of monocrystalline are separated from other such regions by ROI regions 16. The emitter base region is also surface-isolated from the collector region by ROI region 18.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 57% of the total text.

Page 1 of 2

Railless Bipolar Process

In the current process, the extrinsic base polysilicon is defined by reactive ion etching (RIE). Polysilicon rails are left behind near the steps especially the back of the "bird's head" of recessed oxide isolation (ROI). Extensive overetch is required during RIE to remove these rails. The overetch also removes the insulation layer, such as silicon dioxide (SiO2), due to the finite etch rate ratio during RIE. As a result, the final topology is difficult to predict. The process starts by first forming the usual structure of a substrate 10, an epitaxial layer 14 over substrate 10 and a subcollector layer 12. Regions of monocrystalline are separated from other such regions by ROI regions 16. The emitter base region is also surface-isolated from the collector region by ROI region 18. The following process will take care of the above-mentioned problems: 1. A layer 20 of low pressure chemical vapor deposited (LPCVD) SiO2 of 500 nanometers is put down as the CVD underlayer. 2. In-situ doped P+ polysilicon layer 22 is deposited onto the underlayer 20. 3. Photolithography techniques are used to form a mask opening over the designated emitter-base area. 4. The uncovered polysilicon layer 22 is removed and then a 7.1 buffered hydrofluoric acid (BHF) solution is used to etch off the silicon dioxide layer 20. 5. LPCVD polysilicon layer 24 of 350 nanometers is deposited over the structure to obtain the Fig. 1 structure. 6. The wafer is then subjected t...