Browse Prior Art Database

Current Switch-Emitter Follower Compatible Long Delay Circuit

IP.com Disclosure Number: IPCOM000041294D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 45K

Publishing Venue

IBM

Related People

Freeman, LB: AUTHOR [+2]

Abstract

This article describes a circuit with an input-to-output propagation delay an order of magnitude larger than that which would ordinarily be obtained from a standard current switch-emitter follower (CS-EF) circuit. The input and output impedance, signal swings and levels, and device types and sizes are compatible with standard CS-EF circuits, allowing the long delay circuit to be easily integrated into a CS-EF logic chip. In addition, the circuit has a delay variation smaller than the variation associated with conventional CS-EF circuits, leading to improved system performance. The circuit schematic shows a typical embodiment of the concepts involved in making the long delay circuit.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

Current Switch-Emitter Follower Compatible Long Delay Circuit

This article describes a circuit with an input-to-output propagation delay an order of magnitude larger than that which would ordinarily be obtained from a standard current switch-emitter follower (CS-EF) circuit. The input and output impedance, signal swings and levels, and device types and sizes are compatible with standard CS-EF circuits, allowing the long delay circuit to be easily integrated into a CS-EF logic chip. In addition, the circuit has a delay variation smaller than the variation associated with conventional CS-EF circuits, leading to improved system performance. The circuit schematic shows a typical embodiment of the concepts involved in making the long delay circuit. The key features to its operation are the series base resistors 1 and 2, the collector-base feedback provided by transistors 3, 4, 5, 6 and 7, the input loadings provided by transistors 8 and 9, and the double-phase inversion.

1

Page 2 of 2

2

[This page contains 3 pictures or other non-text objects]