Browse Prior Art Database

On-Chip Voltage Regulator

IP.com Disclosure Number: IPCOM000041297D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 67K

Publishing Venue

IBM

Related People

Culican, EF: AUTHOR [+3]

Abstract

The regulator circuit enables the chip to use either one of two power supplies to drive the receiver circuits (not shown) and driver circuits. The two supplies, for example, are 5.0 and 3.4 volts. The I/O (receiver and driver) circuits are designed to operate at the lower supply voltage (3.4 volts). During high supply (5-volt) operation (Fig. 1) the regulator acts as a clamp which generates a reference voltage on line (A) at a potential of 1VBE greater than the I/O operating voltage (3.4 volts). Each I/O cell contains a transistor (T1) which drops the voltage to the desired potential at the driver and receiver circuits. This technique is employed to minimize the current flowing through the reference line. During low supply (3.4-volt) operation, as depicted in Fig.

This text was extracted from a PDF file.
At least one non-text object (such as an image or picture) has been suppressed.
This is the abbreviated version, containing approximately 100% of the total text.

Page 1 of 2

On-Chip Voltage Regulator

The regulator circuit enables the chip to use either one of two power supplies to drive the receiver circuits (not shown) and driver circuits. The two supplies, for example, are 5.0 and 3.4 volts. The I/O (receiver and driver) circuits are designed to operate at the lower supply voltage (3.4 volts). During high supply (5-volt) operation (Fig. 1) the regulator acts as a clamp which generates a reference voltage on line (A) at a potential of 1VBE greater than the I/O operating voltage
(3.4 volts). Each I/O cell contains a transistor (T1) which drops the voltage to the desired potential at the driver and receiver circuits. This technique is employed to minimize the current flowing through the reference line. During low supply (3.4- volt) operation, as depicted in Fig. 2, the regulator is disconnected and each transistor T1 is shorted out. This results in the low supply being directly applied to the driver and receiver circuits. The disclosed technique enables a single set of I/O circuits to be used with two different power supplies. This minimizes design time, saves silicon space, and renders the chip more versatile.

1

Page 2 of 2

2

[This page contains 7 pictures or other non-text objects]