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Driver Circuit

IP.com Disclosure Number: IPCOM000041301D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 39K

Publishing Venue

IBM

Related People

Banker, DC: AUTHOR [+4]

Abstract

To prevent race conditions within latch circuits * , a clock driver must reliably generate a two-phase skewed output under conditions of both fast and very slow input rise times. The fast rise time occurs during normal computer operation, while the slow rise time originates during a testing operation. A common technique of obtaining the skewed output necessary to guarantee hazard-free latch operation is to generate the C1 output through a direct coupled inverter (DCI) (Fig. 1) having a switching threshold higher than that of transistor-transistor logic (TTL) circuits. This higher threshold produces late turn-on of the circuit which drives the C1 output, regardless of input transition time. Unfortunately, the base-emitter diode of the DCI produces a clamping action and reduces up level at the C2 output. The circuit of Fig.

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Driver Circuit

To prevent race conditions within latch circuits * , a clock driver must reliably generate a two-phase skewed output under conditions of both fast and very slow input rise times. The fast rise time occurs during normal computer operation, while the slow rise time originates during a testing operation. A common technique of obtaining the skewed output necessary to guarantee hazard-free latch operation is to generate the C1 output through a direct coupled inverter (DCI) (Fig. 1) having a switching threshold higher than that of transistor-transistor logic (TTL) circuits. This higher threshold produces late turn-on of the circuit which drives the C1 output, regardless of input transition time. Unfortunately, the base-emitter diode of the DCI produces a clamping action and reduces up level at the C2 output. The circuit of Fig. 2 fulfills the above requirements without producing up-level clamping of the C2 output and the consequent reduction in up-level noise tolerance. Clamping is avoided by incorporating a series resistor R1 in the base circuit of the inverter transistor which provides the C1 output. References (*) Representative latch circuits are shown and described in the following: E. B. Eichelberger and T. W. Williams, "A Logic Design Structure For LSI Testability," 14th Design Automation Conference Proceedings, pages 462- 468, June 20, 21 and 22, 1977, New Orleans, Louisiana. IEEE Catalog Number 77, CH1216-1C; and P. Goel and M. T. McMahon, "Elec...