Browse Prior Art Database

Ring Oscillator With Improved Reliability

IP.com Disclosure Number: IPCOM000041308D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 48K

Publishing Venue

IBM

Related People

Maley, GA: AUTHOR

Abstract

Present ring oscillators are constructed from an odd number of inverters connected in a continuous ring. Since there is an odd number of inverters in the ring, the ring is basically unstable and will oscillate. Presently, we measure the frequency of these oscillators, divide by the number of inverters in the ring, and hopefully determine the AC capability of a single logic block. Oscillators of this design are unreliable for they can oscillate in a multi-mode, and furthermore logic blocks in the chain may not fully switch but their output can be amplified and passed on, giving a false high speed reading. Fig. 1 is a block diagram of the disclosed ring oscillator. The delay element, which will be implemented from a string of inverters, is tapped at several points along its length.

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Ring Oscillator With Improved Reliability

Present ring oscillators are constructed from an odd number of inverters connected in a continuous ring. Since there is an odd number of inverters in the ring, the ring is basically unstable and will oscillate. Presently, we measure the frequency of these oscillators, divide by the number of inverters in the ring, and hopefully determine the AC capability of a single logic block. Oscillators of this design are unreliable for they can oscillate in a multi-mode, and furthermore logic blocks in the chain may not fully switch but their output can be amplified and passed on, giving a false high speed reading. Fig. 1 is a block diagram of the disclosed ring oscillator. The delay element, which will be implemented from a string of inverters, is tapped at several points along its length. The reason for these taps is to insure that the entire delay element gets flushed to all 1's and then to all 0's. The latch holds the old value while the delay is flushing. Reference is made to Figs. 1 and 3. Assume that the latch has just been set to a "1" and this "1" will start passing down the delay element. The upper AND gate will not respond with a "1" output until all tap points have reached a full value "1". When the output of the AND does move to a "1", it will reset the latch to a "0" output. This "0" value will enter the delay element and when it reaches the first tap, the output of the AND will drop; thus the reset to latch is removed...