Browse Prior Art Database

Reliability Monitor

IP.com Disclosure Number: IPCOM000041321D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 41K

Publishing Venue

IBM

Related People

Heimeier, H: AUTHOR [+4]

Abstract

A test method and a circuit are described which permit improved reliability forecasts for integrated memory chips. The quality of electronic systems (for example, computers) depends on the function and particularly on the reliability of each individual component. To ensure that semiconductor chips meet specified reliability data, they have to be constantly tested. For this purpose, samples are taken from a batch of chips and life-tested. Such tests consume much time (more than 1000 hours), so that it frequently happens that hardware produced during the performance of the tests has to be scrapped. In addition, such tests are very expensive, as only good chips are used in great quantities. Finally, the chips to be tested have to be mounted on special substrates, as they have to be powered during the 1000-hour life test.

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Reliability Monitor

A test method and a circuit are described which permit improved reliability forecasts for integrated memory chips. The quality of electronic systems (for example, computers) depends on the function and particularly on the reliability of each individual component. To ensure that semiconductor chips meet specified reliability data, they have to be constantly tested. For this purpose, samples are taken from a batch of chips and life-tested. Such tests consume much time (more than 1000 hours), so that it frequently happens that hardware produced during the performance of the tests has to be scrapped. In addition, such tests are very expensive, as only good chips are used in great quantities. Finally, the chips to be tested have to be mounted on special substrates, as they have to be powered during the 1000-hour life test. To eliminate these disadvantages, a test method meeting the following requirements would be desirable: 1. It should be possible to provide sound reliability data or the for the tested hardware within a

few hours. 2. The test should extend to perfect hardware as well as

to hardware with single-cell defects. 3. The test should be implementable on the wafer level. As the reliability of MTL (merged transistor logic) arrays, for example, is largely dependent on the stability of the current amplification (b up) of the inversely operated cell transistors, a special circuit was implemented on chip during the design phase. By means of this circuit, cells for which the current amplification has reached a critical limit are detected at an early stage during regular testing. Such critical cells become inoperative if the cell current drops below a particular value. The absolute magnitude of this value is of minor importance for testing and only changes in it affect the stress test (baking) to be performed. The circuit principle will be described by means of the illustrated example. For adjusting the cell current, other circuits are equally conceivable. The figure shows the generator circuit fo...