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Address Phase Splitter

IP.com Disclosure Number: IPCOM000041327D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 46K

Publishing Venue

IBM

Related People

Berger, R: AUTHOR [+4]

Abstract

For reading or writing a random-access memory (RAM) or for reading a read-only memory (ROM), the addresses, whose contents are to be written or read, are selected. This is done by binary coded address lines. The information of these lines is decoded in the phase splitter and decoder circuits on the chip, in order to select the associated word or bit line. The time necessary for decoding is directly reflected by the access time of the memory chip. During the switching of a conventional phase splitter, a faulty selection, regardless of how short it is, must be avoided; otherwise, the falsely selected bit or word line and the connected cells have to be restored to their original standby potentials before reading or writing.

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Address Phase Splitter

For reading or writing a random-access memory (RAM) or for reading a read- only memory (ROM), the addresses, whose contents are to be written or read, are selected. This is done by binary coded address lines. The information of these lines is decoded in the phase splitter and decoder circuits on the chip, in order to select the associated word or bit line. The time necessary for decoding is directly reflected by the access time of the memory chip. During the switching of a conventional phase splitter, a faulty selection, regardless of how short it is, must be avoided; otherwise, the falsely selected bit or word line and the connected cells have to be restored to their original standby potentials before reading or writing. The drawing shows a phase splitter whose output signals are timed such that a faulty selection of the decoder is avoided. The transistors T2, T5 and T3, T4 together with their current sources T11/T12 and T13/T14 form a first and a second current switch, respectively. The inputs of the second current switch are connected in parallel to the first current switch. T1 and T6 serve to shift the potential of the input level or the reference voltage VBB. Input circuit oscillations are suppressed by the resistor R1. T8, together with the decoupling transistor T17, forms a gate for the output transistor T10. T9, T18 and T7 operate analogously to these transistors. The voltage source V3 serves to adjust the switching level of the gat...