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Low-Voltage CMOS Logic

IP.com Disclosure Number: IPCOM000041328D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 35K

Publishing Venue

IBM

Related People

Haug, W: AUTHOR [+2]

Abstract

A basic building block for CMOS logic families allows much lower voltage swings than a conventional block. The delays and the dissipated power (overlap and AC power) are significantly reduced, and the noise factor is improved. This basic building block comprises two series-connected complementary FETs T1, T2 which form a standard inverter. The high tolerance of the FET threshold voltages VT is one of the greatest problems with FET logic circuits. The essential feature of the inverter is that its overdrives for the N- and P-channel FETs are threshold voltage independent, thus preventing the threshold voltage tolerances from adversely affecting the circuit delays. This is accomplished by feeding the inverter with a threshold voltage dependent supply voltage VB.

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Low-Voltage CMOS Logic

A basic building block for CMOS logic families allows much lower voltage swings than a conventional block. The delays and the dissipated power (overlap and AC power) are significantly reduced, and the noise factor is improved. This basic building block comprises two series-connected complementary FETs T1, T2 which form a standard inverter. The high tolerance of the FET threshold voltages VT is one of the greatest problems with FET logic circuits. The essential feature of the inverter is that its overdrives for the N- and P-channel FETs are threshold voltage independent, thus preventing the threshold voltage tolerances from adversely affecting the circuit delays. This is accomplished by feeding the inverter with a threshold voltage dependent supply voltage VB. This supply voltage is generated on chip by a two-stage N-channel feedback FET circuit with FETs T3 to T6, voltage supply VH, and voltage divider circuit R1, R2 supplying reference voltage VR. The threshold dependent supply voltage is VB N VR + VTN, where VTN is the N-channel threshold voltage of FET T3. T6 supplies and T5 sinks a DC current, in order to recharge the external decoupling capacitor CD which is discharged primarily by load capacitance CL. The voltage generator may be designed as a low power generator, as CMOS circuits do not require a high DC current. Lowering the power supply voltage reduces delays and avoids breakdown problems with future technologies.

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