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Synchronizing Circuit

IP.com Disclosure Number: IPCOM000041335D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 43K

Publishing Venue

IBM

Related People

Sato, F: AUTHOR [+2]

Abstract

The present circuit obtains accurate synchronization with an input data stream from a high speed coaxial link wherein the data stream is coded so that a negative-going transition at the center of a bit cell represents a binary one while a positive-going transition at the center represents a binary zero. In the sync mode, the circuit is phase locked to data transitions. In the async mode, however, it is phase locked to a sync pattern in the data stream. The input data stream on high speed coaxial link 10 is received by shift register 12 having four bit positions D0, D1, D2 and D3. The bit rate of the data stream is 2.36 Mb/s, while the basic clock of the circuit is 14.1523 MHz. Control logic 14 monitors the contents of shift register 12 and controls Johnson counter 16 having three bit positions C0, C1 and C2.

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Synchronizing Circuit

The present circuit obtains accurate synchronization with an input data stream from a high speed coaxial link wherein the data stream is coded so that a negative-going transition at the center of a bit cell represents a binary one while a positive-going transition at the center represents a binary zero. In the sync mode, the circuit is phase locked to data transitions. In the async mode, however, it is phase locked to a sync pattern in the data stream. The input data stream on high speed coaxial link 10 is received by shift register 12 having four bit positions D0, D1, D2 and D3. The bit rate of the data stream is 2.36 Mb/s, while the basic clock of the circuit is 14.1523 MHz. Control logic 14 monitors the contents of shift register 12 and controls Johnson counter 16 having three bit positions C0, C1 and C2. Johnson counter 16 operates as a "divide by 6" counter in the sync mode and as a "divide by 5 (or 7)" counter in the async mode. Its operational sequence is shown in Fig. 2. Control logic 14 detects a transition whenever the contents of shift register 12 become either 1100 or 0011. If the transition is detected during the async mode, control logic 14 loads the content of D0 bit position into Johnson counter 16 so that the circuit is synchronized with the sync pattern in the input data stream from link 10. The circuit is switched to the sync mode when two binary ones are continuously detected in the data stream without a code violation, w...