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Transient Area Handling for a Multi-Level Multiprocessor Operating System

IP.com Disclosure Number: IPCOM000041341D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 1 page(s) / 11K

Publishing Venue

IBM

Related People

Abraham, RL: AUTHOR [+3]

Abstract

Two processors of identical architecture, sharing main storage backed by bulk storage, combine to form a multiprocessor in a manner that permits relatively unconstrained task sharing between the processors. The architecture of each processor is such as to accommodate a uniprocessor configuration in which a fixed logical storage area is dedicated to transient programs, permanently resident in bulk storage and called into variable physical storage areas in main storage when required.

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Transient Area Handling for a Multi-Level Multiprocessor Operating System

Two processors of identical architecture, sharing main storage backed by bulk storage, combine to form a multiprocessor in a manner that permits relatively unconstrained task sharing between the processors. The architecture of each processor is such as to accommodate a uniprocessor configuration in which a fixed logical storage area is dedicated to transient programs, permanently resident in bulk storage and called into variable physical storage areas in main storage when required. To avoid the architecturally fixed transient logical storage area becoming a translation bottleneck if priority forced task switching requires one transient program to supercede another, for transient programs, the physical storage address of the transient program specified by a task is retained in the task control block for that task, whence it is transferred to the translation mechanism when the task becomes active. In the multiprocessor configuration, not only is main storage shared but, also, per force, the translation mechanism or free task sharing becomes less practical. To avoid the fixing of the transient logical storage area again becoming a translation bottleneck, each processor is provided with a private transient storage offset which enables the architecturally defined logical transient storage area to present a private transient identity to the translation mechanism for each processor.

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