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Battery Back-Up With Defined Input Level

IP.com Disclosure Number: IPCOM000041347D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 3 page(s) / 38K

Publishing Venue

IBM

Related People

Groves, JO: AUTHOR [+2]

Abstract

The circuit shown provides input voltage to random-access memory (RAM) 1 at a defined level equal to the source voltage Vi while having battery 3 as an auxiliary or back-up source of power. Diode 5 isolates battery 3 when Vi is at normal level. Diode 7 isolates battery 3 from circuit elements other than RAM 1. Inductor 9 is alternately driven and allowed to discharge in oscillations controlled by transistor 11. Inductor 9 charges capacitor 13, across RAM 1, until the potential across capacitor 13 is at Vi, after which coil 9 is shunted through diode 14. The other circuit elements constitute an oscillator to control transistor 11. Low power memories, such as complementary metal oxide semiconductor (CMOS) memories, can be supported by batteries when in an unaccessed mode, but require substantial currents when in use.

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Battery Back-Up With Defined Input Level

The circuit shown provides input voltage to random-access memory (RAM) 1 at a defined level equal to the source voltage Vi while having battery 3 as an auxiliary or back-up source of power. Diode 5 isolates battery 3 when Vi is at normal level. Diode 7 isolates battery 3 from circuit elements other than RAM 1. Inductor 9 is alternately driven and allowed to discharge in oscillations controlled by transistor 11. Inductor 9 charges capacitor 13, across RAM 1, until the potential across capacitor 13 is at Vi, after which coil 9 is shunted through diode
14. The other circuit elements constitute an oscillator to control transistor 11. Low power memories, such as complementary metal oxide semiconductor (CMOS) memories, can be supported by batteries when in an unaccessed mode, but require substantial currents when in use. This requirement makes it undesirable to supply normal operating current from batteries. Memories are operated from main power normally, while batteries are used as auxiliary power sufficient to protect data stored in memory upon loss of main power. A battery is connected across the memory, such as RAM 1, in series with a diode connected to normally isolate the battery, such as diode 5. If most circuit elements are not promptly isolated from the battery on the loss of main power, the battery will be quickly discharged. A diode can be inserted between the memory and main power poled to isolate the battery. This provides the necessary isolation, but at the cost of the forward-bias drop when main power is up, typically 0.7 volt. A typical input potential, Vi, is 5 volts. Thus, the forward drop would result in memory operation at a voltage 14% lower than main power, usually an unacceptable condition. Where a voltage higher than the desired main power is also available, circuits can be designed in which the higher voltage is divided to provide a memory with a voltage at the level required. This requires precise circuit components, and added power is dissipated in dividing the higher voltage. The circuit shown applies Vi across capacitor 13 while Vi is high. Vi is connected from line 15 through a 510-ohm resistor 17, through then-forward biased diode 19 to gate transistor 11 on. (The 510-ohm resistor 21 provides a path to ground for insuring that transistor 11 is switched off.) With transistor 11 on, current begins to flow through 3-ohm resistor 23 and coil 9, and through transistor 11 to ground. Since 3 ohms is quite small, current in coil 9 increases substantially linearly with time. When the current through resistor 23 rises to provide a threshold drop (typically 0.7 volt) across the emitter-to-base junct...