Browse Prior Art Database

Inverting/Non-Inverting On-Chip CMOS Line Driver

IP.com Disclosure Number: IPCOM000041348D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Bansal, JP: AUTHOR

Abstract

An inverting line driver is shown in Fig. 1, and a non-inverting line driver is shown in Fig. 2. The inverting line driver consists of two stages, the first stage having the transistor 1 as a P channel FET device and transistor 2 as an N channel FET device serving as a conventional inverting CMOS stage. The gate input for the first stage is connected to the gate of the N channel FET device 3, and the inverted output from node 5 is applied to the N channel FET device 4. When a positive potential is applied to the input gate of the circuit, N channel FET device 2 turns on and P channel FET device 1 turns off, thereby applying a ground potential to node 5. The ground potential is applied to the gate of the N channel enhancement-mode FET device 4, turning it off.

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Inverting/Non-Inverting On-Chip CMOS Line Driver

An inverting line driver is shown in Fig. 1, and a non-inverting line driver is shown in Fig. 2. The inverting line driver consists of two stages, the first stage having the transistor 1 as a P channel FET device and transistor 2 as an N channel FET device serving as a conventional inverting CMOS stage. The gate input for the first stage is connected to the gate of the N channel FET device 3, and the inverted output from node 5 is applied to the N channel FET device 4. When a positive potential is applied to the input gate of the circuit, N channel FET device 2 turns on and P channel FET device 1 turns off, thereby applying a ground potential to node 5. The ground potential is applied to the gate of the N channel enhancement-mode FET device 4, turning it off. The positive potential applied to the gate of the N channel FET device 3 turns it on and thus ground potential is applied to the output node 6 of the circuit. The advantage of the inverting line driver circuit is that the FET device 4 is an N channel device which is capable of approximately three times greater current conduction levels than would a P channel FET device connected in the same position between VDD and node 6. This is because of the approximate factor of three greater charge carrier mobility in the N channel FET device when compared with that for a P channel FET device. The circuit further has the advantage of transient power dissipation in the st...