Browse Prior Art Database

Programmed Clock Synchronization in a Skewed Clock Environment

IP.com Disclosure Number: IPCOM000041360D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 36K

Publishing Venue

IBM

Related People

Stranko, TA: AUTHOR [+2]

Abstract

A service processor must be able to exercise strict control over the entire computing system including starting, stopping, and restarting after stoppage due to a hardware detected failure. A variety of basic clocks is required to handle long and short data path requirements. Stopping these clocks synchronously at the time of a hardware failure, or to perform some system function, is imperative in the preservation of the state of the system or functional unit of the system. Once stopped, the system can be scanned for diagnostic analysis and, after a required system function is performed, the system can be restarted without loss of integrity. System stoppage is performed by the service hardware which, upon receipt of a particular signal from a functional unit, turns on a sync latch/trigger combination.

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Programmed Clock Synchronization in a Skewed Clock Environment

A service processor must be able to exercise strict control over the entire computing system including starting, stopping, and restarting after stoppage due to a hardware detected failure. A variety of basic clocks is required to handle long and short data path requirements. Stopping these clocks synchronously at the time of a hardware failure, or to perform some system function, is imperative in the preservation of the state of the system or functional unit of the system. Once stopped, the system can be scanned for diagnostic analysis and, after a required system function is performed, the system can be restarted without loss of integrity. System stoppage is performed by the service hardware which, upon receipt of a particular signal from a functional unit, turns on a sync latch/trigger combination. The timing of this sync mechanism is such that the latch samples for errors only during the not clock time of the earliest clock seen by the functional unit, and for a duration shorter than the not clock time, to prevent the latch from turning on too late and causing the clocks which are intended to be stopped from glitching. After the earliest clock is stopped, the other pre-specified clocks are stopped by using the output of the same latch after going through either fixed (wired) delays or programmable delay chips. The trigger in the latch/trigger combination serves as a feedback device once the signal...