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Adjustable Power-On-Reset Circuit in Mosfet Technology

IP.com Disclosure Number: IPCOM000041367D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 47K

Publishing Venue

IBM

Related People

Cranford, HC: AUTHOR [+2]

Abstract

This article describes an adjustable power on reset (POR) circuit suitable for use on an integrated circuit chip. A pair of depletion-mode FET devices are coupled between the VDD power supply and ground. The FET devices set a reference voltage which is transferred through a pair of enhancement-mode devices to establish a POR function on the chip. Fig. 1 depicts the power on reset circuit, while Fig. 2 shows a timing diagram for the circuit of Fig. 1. Fig. 2 is labeled to correlate with Fig. 1. The circuit initially tracks power supply (VDD) as it is brought up from 0 volts. The tracking characteristics are achieved because depletion-mode device Q5 (depletion-mode devices depicted with a shading between the gate electrode and the device) is on while enhancement-mode device Q6 is off. Device Q3 is also initially off.

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Adjustable Power-On-Reset Circuit in Mosfet Technology

This article describes an adjustable power on reset (POR) circuit suitable for use on an integrated circuit chip. A pair of depletion-mode FET devices are coupled between the VDD power supply and ground. The FET devices set a reference voltage which is transferred through a pair of enhancement-mode devices to establish a POR function on the chip. Fig. 1 depicts the power on reset circuit, while Fig. 2 shows a timing diagram for the circuit of Fig. 1. Fig. 2 is labeled to correlate with Fig. 1. The circuit initially tracks power supply (VDD) as it is brought up from 0 volts. The tracking characteristics are achieved because depletion-mode device Q5 (depletion-mode devices depicted with a shading between the gate electrode and the device) is on while enhancement-mode device Q6 is off. Device Q3 is also initially off. Depletion devices Q1 and Q2 are connected between VDD and ground and act as a voltage divider. The voltage at node 1 is determined by the ratio of these two devices. These devices are sized so that as VDD approaches its final "on" value, the voltage of node 1 reaches a value to turn Q3 on and charge up node 2 to the value necessary to turn on Q6. Providing that Q3 is off, node 2 is held at ground by the pull-down device Q4. This ensures that device Q6 will not conduct. As VDD increases, node 1 eventually rises to a threshold above node 2 and Q3 begins to conduct. As can be seen from the timing diag...