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Content-Addressable Memory Cell Having Only Six Transistors

IP.com Disclosure Number: IPCOM000041384D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Aipperspach, AG: AUTHOR [+2]

Abstract

A content-addressable memory (CAM) cell has a four-FET latch and only two transfer FETs. The gates of the transfer FETs are connected to complementary write/compare lines for each word. The drawing shows a matrix of CAM cells and their peripheral circuits. A typical matrix size is 128 cells wide (128 words) by 20 cells high (20 bits/word). During standby, all write/compare lines W1-W4 are at ground potential, and all bit-compare lines are precharged to +8.5V via FETs such as 7 and 8. A 20-bit input word is simultaneously compared with all 128 stored words in the column dimension. If a match occurs, the bit-line pair corresponding to that column (e.g., B1, B2) remain precharged high. A miscompare discharges the bit-line pair.

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Content-Addressable Memory Cell Having Only Six Transistors

A content-addressable memory (CAM) cell has a four-FET latch and only two transfer FETs. The gates of the transfer FETs are connected to complementary write/compare lines for each word. The drawing shows a matrix of CAM cells and their peripheral circuits. A typical matrix size is 128 cells wide (128 words) by 20 cells high (20 bits/word). During standby, all write/compare lines W1-W4 are at ground potential, and all bit-compare lines are precharged to +8.5V via FETs such as 7 and 8. A 20-bit input word is simultaneously compared with all 128 stored words in the column dimension. If a match occurs, the bit-line pair corresponding to that column (e.g., B1, B2) remain precharged high. A miscompare discharges the bit-line pair. To write data into the matrix, the WRITE signal goes high, complementing the data inputs D0-D1 via exclusive-OR (XOR) buffers. Precharge signal PR then falls, leaving bit lines B1-B4 precharged to 8.5
V. Write/compare lines W1-W4 are driven high or remain at ground, depending upon the state of inputs D0-D1. For example, to write D0=0, D1=1 into column 1, W1=1, W2=0, W3=0, W4=1. The column-1 decoder turns on FETs 10, 12, and 14, discharging B1 and B2 to ground. Node B falls to ground, while node A rises to a 1 level via load FET 1. Similarly, node C discharges and node D rises. The remaining cells simply do a read operation, since their bit lines are not forced to ground. For a compar...