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Planar Area Definition Using Two-Level Self-Aligned Insulation Scheme

IP.com Disclosure Number: IPCOM000041397D
Original Publication Date: 1984-Jan-01
Included in the Prior Art Database: 2005-Feb-02
Document File: 2 page(s) / 80K

Publishing Venue

IBM

Related People

Forster, T: AUTHOR [+3]

Abstract

In the fabrication of Josephson tunnel devices well-defined junction dimensions and impedance levels are the key for proper operation of circuits employing such devices. Described is a technique to produce Nb-based planar Josephson junctions in which the area definition is done using a thin insulating film (Nb2O5). The required insulator thickness is obtained by depositing a second insulating film (SiO) which is self-aligned to the first one. The proposed technique is illustrated in the figures showing the successive process steps used to produce a Nb Josephson junction. The example chosen also demonstrates how insulated metal-edge crossings can be provided.

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Planar Area Definition Using Two-Level Self-Aligned Insulation Scheme

In the fabrication of Josephson tunnel devices well-defined junction dimensions and impedance levels are the key for proper operation of circuits employing such devices. Described is a technique to produce Nb-based planar Josephson junctions in which the area definition is done using a thin insulating film (Nb2O5). The required insulator thickness is obtained by depositing a second insulating film (SiO) which is self-aligned to the first one. The proposed technique is illustrated in the figures showing the successive process steps used to produce a Nb Josephson junction. The example chosen also demonstrates how insulated metal-edge crossings can be provided. After deposition of the base electrode (Nb) on a substrate, holes are etched into the Nb film at locations where subsequent metallization (such as counter-electrode or control lines) will cross the base electrode edge (Fig. 1). This step is necessary in order to provide an insulator-covered edge at these locations. Then, the substrate is patterned with a resist stencil (Fig. 2) for junction area definition by anodization. Any photoresist with an undercut profile can be used at this step, with the requirement that it be resistant against the electrolytic solution. After anodization, during which an Nb- oxide layer (Nb2O5) of, e.g., 500 A thickness, is grown (Fig. 3), the self-aligned deposition of SiO is done through the same stencil (Fig. 4...